為何那麼多女人不想結婚
Verilog While loop,For loop is synthesisable???? [ 理由是 ]:結了婚,我不再是情人,也不再重要,我只是一個黃臉婆。我不願意被冷落。[ 理由是 ]:結了婚,我的地位遠遠落後你家的每一個人,我再也得不到關愛的眼神。[ 理由是 ]:結了婚,所有親友的問候語就會變成:什麼時候生小孩啊?我不要for loop verilog synthesis It is synthesizable but it is always advised that for loops are not to be used in RTL coding. This is because it consumes lot of resources (like area etc.etc) . However u can use it in behavioral coding becuse we do not synthesi...
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