D flip-flop - EDA Playground
Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. ... [2014-08-09 18:03:05 EDT] vlib work && vlog '-timescale' '1ns/1ns' '-sv2k9' design.sv testbench.sv && vsim -c -do "vsim +access+r; run -all; exit"...