MIPI D-PHY Module for Prototype Development | Arasan Chip Systems
Diagram Features Silicon-proven MIPI D-PHY Protocol layer Tested with CSI-2 (Tx & Rx) and DSI (Tx & Rx) High speed (80Mbps to 1.5Gbps per lane) support Low power (at 10Mbps) support 4 data lanes Connectivity to D-PHY through PPI Interface Continuous and ....