MIPI Data Lanes FSA644 Processor - Power Management IC and Semiconductor Company | Fairchild
To meet the MIPI D-PHY Rev 1.1 specification, the edge rate out of the switch must not exceed 233 ps (0.35*UI) to meet the 1.5 Gbps interoperability mask. Figure 5 illustrates the analog switch as part of the MIPI Transmission Line Interconnect System (TL...