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Building Zynq Accelerators with Vivado High Level Synthesis

© Copyright 2013 Xilinx . #include“top.h” #include“ap_interfaces.h” void top(AXI_STREAM& src_axi, AXI_STREAM& dst_axi, int rows, int cols){ //Create AXI streaming interfaces for the core #pragma HLS RESOURCE core=AXIS variable=src_axi metadata="-bus ......

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