J -15 Design Guidelines of Steep Subthreshold TFET to Minimize Energy of Logic Circuits
Design Guidelines of Steep Subthreshold TFET to Minimize Energy of Logic Circuits Hiroshi Fuketa1, Kazuaki Yoshioka1, Koichi Fukuda2, Takahiro Mori2, Hiroyuki Ota2, Makoto Takamiya1, and Takayasu Sakurai1 1 University of Tokyo 2 Green ......