List of designs using Altera External Memory IP - Altera Wiki
Designs by FPGA Family Stratix V Design Example: Stratix V Six Dual Rank DDR3 SRAM UniPHY 667MHz x72 ; SV UniPHY, DDR3 667MHz, Quartus 13.0 Design Example: Stratix V QDR II+ SRAM UniPHY 550 MHz x18 using external PLL ; SV UniPHY ......